For example, Japanese Unexamined Patent Application Publication No. 2008-136030 discloses a clock signal distributing device of a tree structure configured to distribute clock signals in the same phase as illustrated in FIG. 1. In the drawing, a phase locked loop (PLL) circuit 101 includes a circuit block 102, a voltage control oscillator (VCO) 103 and a frequency divider (FDIV) 104 to input a reference clock signal RCK and output a desired clock signal. The circuit block 102 includes a phase frequency detector (PFD), a charge pump (CP) and a low pass filter (LP). The clock signal which is output from the PLL circuit 101 is distributed to a circuit 106 via a buffer 105 of a tree structure. However, in distribution of high frequency clock signals, such a problem may occur that limited driving capability of the buffer 105 causes a variation in phase among the clock signals and an increase in consumption power.
For example, Japanese Unexamined Patent Application Publication No. 2007-82158 discloses another clock signal distributing device using a distributed VCO as illustrated in FIG. 2. In the drawing, a circuit block 201 includes a phase frequency detector (PFD), a charge pump (CP) and a low pass filter (LP) to input an output signal from a frequency divider 202 and a reference clock signal RCK and to output bias signals to three LC resonant oscillators 203. The frequency divider 202 divides the frequency of an oscillation signal from one LC resonant oscillator 203 and outputs the signal so frequency-divided to the circuit block 201. A feedback circuit including the circuit block 201, the LC resonant oscillator 203 and the frequency divider 202 has a PLL circuit configuration. Resistive elements 204 are connected between oscillation nodes of the respective LC resonant oscillators 203. The oscillation signals from the respective LC resonant oscillators 203 are respectively supplied to circuits 206 via buffers 205.
In addition, for example, Japanese Unexamined Patent Application Publication No. 11-74762 discloses a semiconductor integrated circuit device which includes at least two ring oscillation circuits in each of which a plurality of inverters are connected with one another in a multi-stage ring form and conductive wiring.
Further, for example, Japanese Unexamined Patent Application Publication No. 9-34584 discloses a clock signal distribution circuit which includes a clock distribution output circuit configured to output and distributes a first clock signal which synchronizes with an external clock signal which is input thereinto to each load circuit.
In the clock signal distributing device illustrated in FIG. 2, the oscillation node of each LC resonant oscillator 203 is included in a loop of the PLL circuit. Therefore, kicking back of a signal from the circuit 206 to the LC resonant oscillator 201 may directly affect the characteristic of the PLL circuit. In addition, because of the necessity to distribute the bias signal from the circuit block 201 to each LC resonant oscillator 203, noise may be mixed into the signal and hence the clock signal characteristic may be deteriorated. In addition, because of the necessary to design the PLL circuit together with the distribution circuit of the LC resonant oscillator, the clock signal distributing device of the type illustrated in FIG. 2 has such problems that it is difficult to design the device and arrangement of circuits is greatly limited.